MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 77
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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6.4.5.3 EEPROM-1 Erasing
The programmed state of an EEPROM bit is logic 0. Erasing changes the state to a logic 1. Only
EEPROM-1 bytes in the non-protected blocks and the EE1NVR register can be erased.
Use the following procedure to erase a byte, block or the entire EEPROM-1 array:
Freescale Semiconductor
1. Configure EERAS1 and EERAS0 for byte, block or bulk erase; set EELAT in EE1CR.
2. Byte erase: write any data to the desired address.
3. Set the EEPGM bit.
4. Wait for a time: t
5. Clear EEPGM bit.
6. Wait for a time, t
7. Poll the EEPGM bit until it is cleared by the internal timer.
8. Clear EELAT bits.
Block erase: write any data to an address within the desired block.
Bulk erase: write any data to an address within the array.
If using the AUTO mode, also set the AUTO bit in Step 1.
A. Setting the EELAT bit configures the address and data buses to latch
data for erasing the array. Only valid EEPROM-1 addresses will be latched.
If EELAT is set, other writes to the EE1CR will be allowed after a valid
EEPROM-1 write.
B. If more than one valid EEPROM write occurs, the last address and data
will be latched overriding the previous address and data. Once data is
written to the desired address, do not read EEPROM-1 locations other than
the written location. (Reading an EEPROM location returns the latched data
and causes the read address to be latched).
C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non-valid
EEPROM address is latched. This is to ensure proper programming
sequence. Once EEPGM is set, do not read any EEPROM-1 locations;
otherwise, the current program cycle will be unsuccessful. When EEPGM
is set, the on-board programming sequence will be activated.
D. The delay time for the EEPGM bit to be cleared in AUTO mode is less
than t
may be different. For forward compatibility, software should not make any
dependency on this delay time.
E. Any attempt to clear both EEPGM and EELAT bits with a single
instruction will only clear EEPGM. This is to allow time for removal of high
voltage from the EEPROM-1 array.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
EEBYTE
EEBYTE
EEFPV
(E)
(C)
/t
, for the erasing voltage to fall. Go to Step 8.
Go to Step 7 if AUTO is set.
EEBLOCK
for byte erase; t
/t
EEBULK
. However, on other MCUs, this delay time
EEBLOCK
NOTE
NOTE
for block erase; t
(B)
(B)
(D)
EEBULK.
(B)
for bulk erase.
Functional Description
(A)
77
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