MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 357
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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DLOOP — Digital Loopback Mode Bit
RX4XE — Receive 4X Enable Bit
NBFS — Normalization Bit Format Select Bit
TEOD — Transmit End of Data Bit
Freescale Semiconductor
the off-chip analog transceiver is no longer in loopback mode, the BDLC waits for an EOF symbol
before attempting to transmit.
This bit determines the source to which the digital receive input (BDRxD) is connected and can be used
to isolate bus fault conditions (see
control bit allows the programmer to connect the digital transmit output to the digital receive input. In
this configuration, data sent from the transmit buffer will be reflected back into the receive buffer. If no
faults exist in the BDLC, the fault is in the physical interface block or elsewhere on the J1850 bus.
This bit determines if the BDLC operates at normal transmit and receive speed (10.4 kbps) or receive
only at 41.6 kbps. This feature is useful for fast download of data into a J1850 node for diagnostic or
factory programming of the node.
This bit controls the format of the normalization bit (NB). (See Figure 27-18.) SAE J1850 strongly
encourages using an active long (logic 0) for in-frame responses containing cyclical redundancy check
(CRC) and an active short (logic 1) for in-frame responses without CRC.
This bit is set by the programmer to indicate the end of a message is being sent by the BDLC. It will
append an 8-bit CRC after completing transmission of the current byte. This bit also is used to end an
in-frame response (IFR). If the transmit shadow register is full when TEOD is set, the CRC byte will be
transmitted after the current byte in the Tx shift register and the byte in the Tx shadow register have
been transmitted. (See
register.) Once TEOD is set, the transmit data register empty flag (TDRE) in the BDLC state vector
register (BSVR) is cleared to allow lower priority interrupts to occur. (See
Register.)
1 = Input to the analog physical interface’s final drive stage is looped back to the BDLC receiver.
0 = The J1850 bus will be driven by the BDLC. After the bit is cleared, the BDLC requires the bus
1 = When set, BDRxD is connected to BDTxD. The BDLC is now in digital loopback mode.
0 = When cleared, BDTxD is not connected to BDRxD. The BDLC is taken out of digital loopback
1 = When set, the BDLC is put in 4X receive-only operation.
0 = When cleared, the BDLC transmits and receives at 10.4 kbps.
1 = NB that is received or transmitted is a 0 when the response part of an in-frame response (IFR)
0 = NB that is received or transmitted is a 1 when the response part of an in-frame response (IFR)
1 = Transmit end-of-data (EOD) symbol
0 = The TEOD bit will be cleared automatically at the rising edge of the first CRC bit that is sent or
The J1850 bus is not driven.
to be idle for a minimum of end-of-frame symbol time (t
minimum of inter-frame symbol time (t
Transmitter VPW Symbol
mode and can now drive the J1850 bus normally.
ends with a CRC byte. NB that is received or transmitted is a 1 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
ends with a CRC byte. NB that is received or transmitted is a 0 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
if an error is detected. When TEOD is used to end an IFR transmission, TEOD is cleared when
the BDLC receives back a valid EOD symbol or an error condition occurs.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
27.5.3 Rx and Tx Shadow Registers
Timings.
Figure
27-13). If a fault condition has been detected on the bus, this
TRV6
) before message transmission. (See
for a description of the transmit shadow
TRV4
) before message reception or a
27.6.4 BDLC State Vector
BDLC CPU Interface
28.1.15 BDLC
357
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