MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 298
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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MSCAN Controller (MSCAN08)
23.13.12 MSCAN08 Identifier Acceptance Registers
On reception each message is written into the background receive buffer. The CPU is only signalled to
read the message, however, if it passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message will be overwritten by the next message (dropped).
The acceptance registers of the MSCAN08 are applied on the IDR0 to IDR3 registers of incoming
messages in a bit by bit manner.
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers only
the first two (CIDMR0/1 and CIDAR0/1) are applied.
AC7–AC0 — Acceptance Code Bits
298
AC7–AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related
identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is
then masked with the corresponding identifier mask register.
CIDAR0 Address: $0510
CIDAR1 Address: $050511
CIDAR2 Address: $0512
CIDAR3 Address: $0513
The CIDAR0–3 registers can be written only if the SFTRES bit in CMCR0
is set
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Figure 23-26. Identifier Acceptance Registers (CIDAR0–CIDAR3)
Bit 7
AC7
Bit 7
AC7
Bit 7
AC7
Bit 7
AC7
AC6
AC6
AC6
AC6
6
6
6
6
AC5
AC5
AC5
AC5
5
5
5
5
NOTE
Unaffected by Reset
Unaffected by Reset
Unaffected by Reset
Unaffected by Reset
AC4
AC4
AC4
AC4
4
4
4
4
AC3
AC3
AC3
AC3
3
3
3
3
AC2
AC2
AC2
AC2
2
2
2
2
AC1
AC1
AC1
AC1
1
1
1
1
Freescale Semiconductor
Bit 0
AC0
Bit 0
AC0
Bit 0
AC0
Bit 0
AC0
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