MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 353
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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27.5.5.5 Summary
27.6 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the BDLC and consists of five user
registers.
Freescale Semiconductor
•
•
•
•
•
BDLC analog and roundtrip delay register (BARD)
BDLC control register 1 (BCR1)
BDLC control register 2 (BCR2)
BDLC state vector register (BSVR)
BDLC data register (BDR)
Transmission Error
Cyclical Redundancy Check (CRC)
Error
Invalid Symbol: BDLC Receives
Invalid Bits (Noise)
Framing Error
Bus Short to V
Bus Short to GND
BDLC Receives BREAK Symbol.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Error Condition
DD
Table 27-1. BDLC J1850 Bus Error Summary
Figure 27-14. BDLC Block Diagram
PROTOCOL HANDLER
PHYSICAL INTERFACE
For invalid bits or framing symbols on non-byte
boundaries, invalid symbol interrupt will be
generated. BDLC stops transmission.
CRC error interrupt will be generated. The BDLC will
wait for SOF.
The BDLC will abort transmission immediately.
Invalid symbol interrupt will be generated.
Invalid symbol interrupt will be generated. The BDLC
will wait for start-of-frame (SOF).
The BDLC will not transmit until the bus is idle.
Thermal overload will shut down physical interface.
Fault condition is reflected in BSVR as an invalid
symbol.
The BDLC will wait for the next valid SOF. Invalid
symbol interrupt will be generated.
CPU INTERFACE
MUX INTERFACE
TO J1850 BUS
TO CPU
BDLC Function
BDLC
BDLC CPU Interface
353
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