MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 73
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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6.4 Functional Description
The 512 bytes of EEPROM-1 are located at $0800-$09FF and can be programmed or erased without an
additional external high voltage supply. The program and erase operations are enabled through the use
of an internal charge pump. For each byte of EEPROM, the write/erase endurance is 10,000 cycles.
6.4.1 EEPROM-1 Configuration
The 8-bit EEPROM-1 Nonvolatile Register (EE1NVR) and the 16-bit EEPROM-1 Timebase Divider
Nonvolatile Register (EE1DIVNVR) contain the default settings for the following EEPROM configurations:
EE1NVR and EE1DIVNVR are nonvolatile EEPROM registers. They are programmed and erased in the
same way as EEPROM bytes. The contents of these registers are loaded into their respective volatile
registers during a MCU reset. The values in these read/write volatile registers define the EEPROM-1
configurations.
For EE1NVR, the corresponding volatile register is the EEPROM-1 Array Configuration Register
(EE1ACR). For the EE1DIVNCR (two 8-bit registers: EE1DIVHNVR and EE1DIVLNVR), the
corresponding volatile register is the EEPROM-1 Divider Register (EE1DIV: EE1DIVH and EE1 DIVL).
6.4.2 EEPROM-1 Timebase Requirements
A 35μs timebase is required by the EEPROM-1 control circuit for program and erase of EEPROM content.
This timebase is derived from dividing the CGMXCLK or bus clock (selected by EEDIVCLK bit in
CONFIG-2 Register) using a timebase divider circuit controlled by the 16-bit EEPROM-1 Timebase
Divider EE1DIV Register (EE1DIVH and EE1DIVL).
As the CGMXCLK or bus clock is user selected, the EEPROM-1 Timebase Divider Register must be
configured with the appropriate value to obtain the 35 μs. The timebase divider value is calculated by
using the following formula:
This value is written to the EEPROM-1 Timebase Divider Register (EE1DIVH and EE1DIVL) or
programmed into the EEPROM-1 Timebase Divider Nonvolatile Register prior to any EEPROM program
or erase operations
Freescale Semiconductor
•
•
•
EE1DIV= INT[Reference Frequency(Hz) x 35 x10
EEPROM-1 Timebase Reference
EEPROM-1 Security Option
EEPROM-1 Block Protection
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
(6.4.1 EEPROM-1 Configuration
-6
and
+0.5]
6.4.2 EEPROM-1 Timebase
Functional Description
Requirements).
73
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