MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 350
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Byte Data Link Controller (BDLC)
27.5.1 Protocol Architecture
The protocol handler contains the state machine, Rx shadow register, Tx shadow register, Rx shift
register, Tx shift register, and loopback multiplexer as shown in
27.5.2 Rx and Tx Shift Registers
The Rx shift register gathers received serial data bits from the J1850 bus and makes them available in
parallel form to the Rx shadow register. The Tx shift register takes data, in parallel form, from the Tx
shadow register and presents it serially to the state machine so that it can be transmitted onto the J1850
bus.
27.5.3 Rx and Tx Shadow Registers
Immediately after the Rx shift register has completed shifting in a byte of data, this data is transferred to
the Rx shadow register and RDRF or RXIFR is set (see
interrupt is generated if the interrupt enable bit (IE) in BCR1 is set. After the transfer takes place, this new
data byte in the Rx shadow register is available to the CPU interface, and the Rx shift register is ready to
shift in the next byte of data. Data in the Rx shadow register must be retrieved by the CPU before it is
overwritten by new data from the Rx shift register.
350
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
DLOOP FROM BCR2
LOOPBACK CONTROL
Figure 27-13. BDLC Protocol Handler Outline
Rx SHADOW REGISTER
Rx SHIFT REGISTER
BDRxD
MULTIPLEXER
LOOPBACK
TO CPU INTERFACE AND Rx/Tx BUFFERS
8
TO PHYSICAL INTERFACE
STATE MACHINE
27.6.4 BDLC State Vector
BDTxD
Figure
Tx SHADOW REGISTER
Tx SHIFT REGISTER
27-13.
8
Register) and an
Freescale Semiconductor
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