MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 341
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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SOF — Start-of-Frame Symbol
Data — In-Message Data Bytes
CRC — Cyclical Redundancy Check Byte
EOD — End-of-Data Symbol
Freescale Semiconductor
IDLE
All messages transmitted onto the J1850 bus must begin with a long-active 200-μs period SOF symbol.
This indicates the start of a new message transmission. The SOF symbol is not used in the CRC
calculation.
The data bytes contained in the message include the message priority/type, message ID byte (typically
the physical address of the responder), and any actual data being transmitted to the receiving node.
The message format used by the BDLC is similar to the 3-byte consolidated header message format
outlined by the SAE J1850 document. See SAE J1850 — Class B Data Communications Network
Interface for more information about 1- and 3-byte headers.
Messages transmitted by the BDLC onto the J1850 bus must contain at least one data byte and,
therefore, can be as short as one data byte and one CRC byte. Each data byte in the message is eight
bits in length and is transmitted MSB to LSB.
This byte is used by the receiver(s) of each message to determine if any errors have occurred during
the transmission of the message. The BDLC calculates the CRC byte and appends it onto any
messages transmitted onto the J1850 bus. It also performs CRC detection on any messages it
receives from the J1850 bus.
CRC generation uses the divisor polynomial X
is set to all ones. Each byte in the message after the start of frame (SOF) symbol is processed serially
through the CRC generation circuitry. The one’s complement of the remainder then becomes the 8-bit
CRC byte, which is appended to the message after the data bytes in MSB-to-LSB order.
When receiving a message, the BDLC uses the same divisor polynomial. All data bytes, excluding the
SOF and end of data symbols (EOD) but including the CRC byte, are used to check the CRC. If the
message is error free, the remainder polynomial will equal X
contained in the message. If the calculated CRC does not equal $C4, the BDLC will recognize this as
a CRC error and set the CRC error flag in the BSVR.
The EOD symbol is a long 200-μs passive period on the J1850 bus used to signify to any recipients of
a message that the transmission by the originator has completed. No flag is set upon reception of the
EOD symbol.
SOF
PRIORITY
(DATA0)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
DATA
MESSAGE
ID (DATA1)
. J1850 Bus Message Format (VPW)
DATA
8
+ X
N
4
+ X
CRC
3
+ X
7
2
+ X
O
E
D
+ 1. The remainder polynomial initially
6
N
+ X
B
OPTIONAL
2
= $C4, regardless of the data
IFR
BDLC MUX Interface
EOF
F
S
I
IDLE
341
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