MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 335
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Chapter 27
Byte Data Link Controller (BDLC)
27.1 Introduction
The byte data link controller (BDLC) provides access to an external serial communication multiplex bus,
operating according to the Society of Automotive Engineers (SAE) J1850 protocol.
The BDLC-D is only available on the MC68HC908AS60A.
27.2 Features
Features of the BDLC module include:
27.3 Functional Description
Figure 27-1
addressable registers and provides the link between the CPU and the buffers. The buffers provide storage
for data received and data to be transmitted onto the J1850 bus. The protocol handler is responsible for
the encoding and decoding of data bits and special message symbols during transmission and reception.
The MUX interface provides the link between the BDLC digital section and the analog physical interface.
The wave shaping, driving, and digitizing of data is performed by the physical interface.
Use of the BDLC module in message networking fully implements the SAE Standard J1850 Class B Data
Communication Network Interface specification.
Freescale Semiconductor
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SAE J1850 class B data communications network interface compatible and ISO compatible for low
speed (<125 kbps) serial data communications in automotive applications
10.4 kbps variable pulse width (VPW) bit format
Digital noise filter
Collision detection
Hardware cyclical redundancy check (CRC) generation and checking
Two power-saving modes with automatic wakeup on network activity
Polling and CPU interrupts available
Block mode receive and transmit supported
Supports 4X receive mode, 41.6 kbps
Digital loopback mode
Analog loopback mode
In-frame response (IFR) types 0, 1, 2, and 3 supported
shows the organization of the BDLC module. The CPU interface contains the software
It is recommended that the reader be familiar with the SAE J1850 document
and ISO Serial Communication document prior to proceeding with this
chapter of the specification.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
NOTE
335
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