MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 348
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Byte Data Link Controller (BDLC)
27.4.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a non-destructive manner, allowing the
message with the highest priority to be transmitted, while any transmitters which lose arbitration simply
stop transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that another message is in progress, it waits
until the bus is idle. However, if multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF symbol and will continue with each
bit thereafter.
The variable pulse width modulation (VPW) symbols and J1850 bus electrical characteristics are chosen
carefully so that a logic 0 (active or passive type) will always dominate over a logic 1 (active or passive
type) that is simultaneously transmitted. Hence, logic 0s are said to be dominant and logic 1s are said to
be recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted a recessive bit, the node loses
arbitration and immediately stops transmitting. This is known as bitwise arbitration.
348
TRANSMITTER A
TRANSMITTER B
J1850 BUS
PASSIVE
PASSIVE
PASSIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PASSIVE
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Figure 27-10. J1850 VPW Received BREAK Symbol Times
Figure 27-11. J1850 VPW Bitwise Arbitrations
SOF
240 μs
DATA
BIT 1
0
0
0
DATA
BIT 2
1
1
1
DATA
BIT 3
1
1
1
e
1
DATA
BIT 4
0
0
DATA
BIT 5
0
0
(2) VALID BREAK SYMBOL
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
TRANSMITTER B WINS
ARBITRATION AND
TRANSMITTING
Freescale Semiconductor
CONTINUES
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