MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 133
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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10.3.2.5 Special Programming Exceptions
The programming method described in
exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these
exceptions:
10.3.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the
Freescale Semiconductor
7. Using the value 4.9152 MHz for f
8. Calculate the VCO center-of-range frequency, f
9. Program the PLL registers accordingly:
•
•
multiplier controls the frequency range of the PLL.
midpoint between the minimum and maximum frequencies attainable by the PLL.
A 0 value for N is interpreted the same as a value of 1.
A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See
10.3.3 Base Clock Selector
a. In the upper four bits of the PLL programming register (PPG), program the binary equivalent
b. In the lower four bits of the PLL programming register (PPG), program the binary equivalent
f
Example: f
CGMVRS
of N.
of L.
For proper operation,.
Exceeding the recommended maximum bus frequency or VCO frequency
can crash the MCU.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
= L
CGMVRS
×
f
NOM
= 7 × 4.9152 MHz = 34.4 MHz
Circuit.
Example:
f
CGMVRS
NOM
10.3.2.4 Programming the
L
=
, calculate the VCO linear range multiplier, L. The linear range
round
–
L
f
=
CGMVCLK
NOTE
------------------------------- -
4.9152 MHz
⎛
⎝
32 MHz
f
----------------------- -
CGMVCLK
CGMVRS
f
NOM
≤
f
--------------- -
NOM
. The center-of-range frequency is the
2
⎞
⎠
=
PLL, does not account for two possible
7
Functional Description
133
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