AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 733

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6062M–ATARM–23-Mar-09
Doc. Rev.
6062D
Date
14-Apr-06
Comments (Continued)
USART:
Table 31-3, “Binary and Decimal Values for Di,” on page 406
Decimal Values for Fi,” on page 406
Figure 31-24, “IrDA Demodulator Operations,” on page 422
TC: Addition of
TC:
“....(EEVT = 0), TIOB is no longer used as an output and the compare register B is not used
to generate waveforms and subsequently no IRQ
in
MCI: Specified reset condition for DCRCE and DTOE bits in
Register” on page
MCI: Update to
with PDC. Addition of
page
UHP: Corrected signal name and corrected ASB bus to ASB bus in
Diagram,” on page 545
LCDC: Corrected typos in signal names in
VPW = 2, VBP = 2, VFP = 1,” on page
LCDC: Removed references to AHB and LCDC clock domains in
Macrocell Block Diagram,” on page
LCDC: Updated
LCDC: Modified signal names throughout to be consistent with device: LCD_VSYNC
changed to LCDVSYNC, LCD_HSYNC changed to LCDHSYNC, LCD_PCLK changed to
LCDDOTCK, LCD_DVAL changed to LCDDEN, LCD_CC changed to LCDCC.
Removed all references to LCD_MOD and LCD_PWR as these signals are not bonded in
the device:
on page
Sequence” on page
”TFT Mode Example” on page
on page 611
Electrical Characteristics: Corrected typ value for R
Characteristics,” on page
Section 33.6.5 ”TC Channel Mode Register: Waveform Mode” on page 504
Section 33.5.12 ”External Event/Trigger Conditions” on page 496
552.
Section 31.5.1 ”I/O Lines” on page
595,
Table 37-1, “I/O Lines Description,” on page
and removed LCDMOD Toggle Rate Value Register.
Section 37.5.2.4 ”Display” on page
Table 33-1, “Timer Counter Clock Assignment,” on page
Figure 35-9, “Write Functional Flow Diagram,” on page 551
Section 37.9 ”Register Configuration Guide” on page
565.
607,
Figure 35-10, “Multiple Write Functional Flow Diagram,” on
to UHPCK.
Section 37.9.1 ”STN Mode Example” on page
635.
610,
586.
Table 37.10, “LCD Controller (LCDC) User Interface,”
DI and Fi properly referenced in titles.
598.
Figure 37-4, “TFT Panel Timing, CLKMOD = 0,
402, text concerning TXD line added.
s.”
600,
AT91SAM9261 Preliminary
PULLUP
Added note
Section 37.7 ”Configuration
587,
in
modified.
Section 35.9.10 “MCI Status
Table 38-2, “DC
and
Section 37.5.2.3 ”Timegen”
(1)
Figure 37-1, “LCD
Table 31-4, “Binary and
to EEVT bit description
Figure 35-1, “Block
new text as follows:
610.
610,
483.
in case of write
Section 37.9.2
.
Change
Request
Reference
2794
2470
2704
2593
2462
2924
2402
2424
2426
2763
2457
733