AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 122
AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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17.6.2
Register Name: SHDW_MR
Address:
Access Type: Read/Write
• WKMODE0: Wake-up Mode 0
• CPTWK0: Counter on Wake-up 0
Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wake-
up event occurs. Because of the internal synchronization of WKUP0, the
(CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP.
• RTTWKEN: Real-time Timer Wake-up Enable
0 = The RTT Alarm signal has no effect on the Shutdown Controller.
1 = The RTT Alarm signal forces the de-assertion of the
122
31
23
15
–
–
7
0
0
1
1
WKMODE[1:0]
AT91SAM9261 Preliminary
Shutdown Mode Register
0xFFFFFD14
30
22
14
–
–
6
0
1
0
1
CPTWK0
–
Wake-up Input Transition Selection
None. No detection is performed on the wake-up input
Low to high level
High to low level
Both levels change
29
21
13
–
–
5
28
20
12
–
–
4
SHDN
pin.
27
19
11
–
–
–
3
–
SHDN
pin is released
26
18
10
–
–
–
2
–
25
17
–
–
9
1
WKMODE0
6062M–ATARM–23-Mar-09
–
RTTWKEN
24
16
–
8
0
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