AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 715

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

42.3.11.2
42.3.11.3
42.3.11.4
42.3.12
42.3.12.1
42.3.13
42.3.13.1
6062M–ATARM–23-Mar-09
Shutdown Controller (SHDWC)
Static Memory Controller (SMC)
SSC: Periodic Transmission Limitations in Master Mode
SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer
SSC: First RK Clock Cycle when Rk Outputs a Clock During Data Transfer
SHDWC: Boundary Scan Mode Outputs the 32 kHz clock
SMC: Chip Select Parameters Modification
If the Least Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not
sent.
None.
When the SSC receiver is used with the following conditions:
At the end of the data, the RK pin is set in high impedance which might be seen as an unex-
pected clock cycle.
Enable the pull-up on RK pin.
When the SSC receiver is used with the following conditions:
The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)).
None.
In boundary scan mode, the SHDN pin outputs tge 32 kHz clock.
There is only one way to disable the 32 kHz clock on the SHDN pin.
In boundary scan mode, connect TST and JTAGSEL pins to VDDBU and set the SHDN pin to
low level.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse,
Cycle, Mode) if accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code
from a memory connected on this CS0, may lead to unpredictable behavior.
The code used to modify the parameters of an SMC Chip Select can be executed from the inter-
nal RAM or from a memory connected to another Chip Select
• the internal clock divider is used (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem/Fix Workaround
Problem Fix/Workaround
AT91SAM9261 Preliminary
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