AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 713

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

42.3.10.2
42.3.10.3
42.3.10.4
42.3.10.5
42.3.10.6
42.3.10.7
6062M–ATARM–23-Mar-09
SPI: Bad PDC behavior when CSAAT=1 and SCBR = 1
SPI: LASTXFER (Last Transfer) Behavior
SPI: Chip Select and fixed mode
SPI: Baudrate set to 1
SPI: Software Reset
SPI: Software Reset Must be Written Twice
Do not use this configuration.
If the SPI2 is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are per-
formed consecutively on the same slave with an IDLE state between them, the second data is
sent twice.
None. Do not use the combination CSAAT=1 and SCBR =1.
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on
the data written in the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes
a "1" in bit 24 (LASTXFER bit) of the SPI_TDR, the Chip Select rises as soon as the TXEMPTY
flag is set.
Use the CS in PIO mode when “PDC mode” is required and CS has to be maintained between
transfers.
In FIXED Mode, if a transfer is performed through a PDC on a Chip Select different from the
Chip Select 0, the output spi_size sampled by the PDC will depend on the field BITS of
SPI_CSR0 register, whatever the selected Chip select is. For example if CSR0 is configured for
a 10-bit transfer whereas the CSR1 is configured for a 8-bit transfer, when a transfer is per-
formed in Fixed mode through the PDC on Chip Select1, the transfer is considered as a halfword
transfer.
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y different from 0), the field
BITS of the CSR0 must be configured in 8 bits in the same way as the field BITS of the CSRy
Register.
When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency),
and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case
9,11,13 or 15), an additional pulse is generated on output SPCK. No problem occurs if BITS field
equals 8,10,12,14 or 16 and Baudrate = 1.
None.
If the Software reset command is performed at the same clock cycle as an event for TXRDY
occurs, there is no reset.
Perform another software reset.
If a software reset (SWRST in the SPI control register) is performed, the SPI may not work prop-
erly (the clock is enabled before the chip select).
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9261 Preliminary
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