AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 628

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

38.5.2.10
38.5.2.11
38.5.3
628
AT91SAM9261 Preliminary
LCD Interface
Display
PWM
HFP
=
f
LCDDOTCK
The line counting is controlled by the read-only field LINECNT of LCDCON1 register. The
LINECNT field decreases by one unit at each falling edge of LCDHSYNC.
This block is used to configure the polarity of the data and control signals. The polarity of all
clock signals can be configured by LCDCON2[12:8] register setting.
This block also generates the lcd_pwr signal internally used to control the state of the LCD pins
and to turn on and off by software the LCD module.
This signal is controlled by the PWRCON register and respects the number of frames configured
in the GUARD_TIME field of PWRCON register (PWRCON[7:1]) between the write access to
LCD_PWR field (PWRCON[0]) and the activation/deactivation of lcd_pwr signal.
The minimum value for the GUARD_TIME field is one frame. This gives the DMA Controller
enough time to fill the FIFOs before the start of data transfer to the LCD.
This block generates the LCD contrast control signal (LCDCC) to make possible the control of
the display's contrast by software. This is an 8-bit PWM (Pulse Width Modulation) signal that can
be converted to an analog voltage with a simple passive filter.
The PWM module has a free-running counter whose value is compared against a compare reg-
ister (CONTRAST_VAL register). If the value in the counter is less than that in the register, the
output brings the value of the polarity (POL) bit in the PWM control register: CONTRAST_CTR.
Otherwise, the opposite value is output. Thus, a periodic waveform with a pulse width propor-
tional to the value in the compare register is generated.
Due to the comparison mechanism, the output pulse has a width between zero and 255 PWM
counter cycles. Thus by adding a simple passive filter outside the chip, an analog voltage
between 0 and (255/256) × VDD can be obtained (for the positive polarity case, or between
(1/256) × VDD and VDD for the negative polarity case). Other voltage values can be obtained by
adding active external circuitry.
For PWM mode, the frequency of the counter can be adjusted to four different values using field
PS of CONTRAST_CTR register.
The LCD Controller interfaces with the LCD Module through the LCD Interface
page
scan, 16-bit STN Dual Scan Mono (Color), 8-bit STN Dual (Single) Scan Mono (Color), 4-bit sin-
gle scan Mono (Color).
A 4-bit single scan STN display uses 4 parallel data lines to shift data to successive single hori-
zontal lines one at a time until the entire frame has been shifted and transferred. The 4 LSB pins
of LCD Data Bus (LCDD [3:0]) can be directly connected to the LCD driver; the 20 MSB pins
(LCDD [23:4]) are not used.
634). The Controller supports the following interface configurations: 24-bit TFT single
×
-------------------------------------------------------------------------------------------------------------- -
f
LCDVSYNC
×
(
LINEVAL
1
+
VBP
+
VFP
+
1
)
–
(
VHDLY
+
VPW
+
VBP
6062M–ATARM–23-Mar-09
+
(Table 38-11 on
HOZVAL
+
5
)