AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 700

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

42.2.9.3
42.2.10
42.2.10.1
42.2.10.2
42.2.10.3
42.2.10.4
700
AT91SAM9261 Preliminary
Serial Peripheral Interface (SPI)
SDRAM: Mobile SDRAM Device Initialization Constraint
SPI: Pulse Generation on SPCK
SPI: Bad PDC behavior when CSAAT=1 and SCBR = 1
SPI: LASTXFER (Last Transfer) Behavior
SPI: Chip Select and fixed mode
Use a fully JEDEC compliant SDRAM module.
Using Mobile SDRAM devices that need to have their DQMx level HIGH during the Mobile
SDRAM device intialization, may lead to data bus contention. Therefore, external memories on
the same EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “don’t care” during this
phase.
Mobile SDRAM initialization must be performed in internal SRAM.
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as
follows:
Do not use this configuration.
If the SPI2 is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are per-
formed consecutively on the same slave with an IDLE state between them, the second data is
sent twice.
None. Do not use the combination CSAAT=1 and SCBR =1.
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on
the data written in the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes
a "1" in bit 24 (LASTXFER bit) of the SPI_TDR, the Chip Select rises as soon as the TXEMPTY
flag is set.
Use the CS in PIO mode when “PDC mode” is required and CS has to be maintained between
transfers.
In FIXED Mode, if a transfer is performed through a PDC on a Chip Select different from the
Chip Select 0, the output spi_size sampled by the PDC will depend on the field BITS of
SPI_CSR0 register, whatever the selected Chip select is. For example if CSR0 is configured for
a 10-bit transfer whereas the CSR1 is configured for a 8-bit transfer, when a transfer is per-
formed in Fixed mode through the PDC on Chip Select1, the transfer is considered as a halfword
transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
– The Baudrate is odd and different from 1.
– The Polarity is set to 1.
– The Phase is set to 0 .
6062M–ATARM–23-Mar-09