AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 718

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

42.3.16
42.3.16.1
42.3.17
42.3.17.1
42.3.17.2
718
AT91SAM9261 Preliminary
UDP
UHP
UDP: Bad data in the first IN data stage
UHP: Non-ISO IN transfers
UHP: ISO OUT transfers
All or part of the data of the first IN data Stage are not transmitted.It may then be a Zero Length
Packet. The CRC is correct. So the HOST may only see that the size of the received data does
not match the requested length. But even if performed again, the control transfer will probably
fail.
These Control transfers are mainly used at device configuration. After clearing RXSETUP, the
software needs to compute the setup transaction request before writing data into the FIFO if
needed. This time is generally greater than the minimum safe delay required above. If not, a
software wait loop after RXSETUP clear may be added at minimum cost
Conditions:
Consider the following sequence:
Consequence: When this defect manifests itself, the Host controller re-attempts the same IN
token.
This problem can be avoided if the system guarantees that the status update can be completed
within the same frame.
Conditions:
Consider the following sequence:
Consequence: After the failure condition, the Host controller stops sending the SOF. This
causes the connected device to go into suspend state.
1. The Host controller issues an IN token.
2. The Device provides the IN data in a short packet.
3. The Host controller writes the received data to the system memory.
4. The Host controller is now supposed to carry out two Write transactions (TD status
5. The Host controller raises the request for the first write transaction. By the time the
6. After completing the first write transaction, the Host controller skips the second write
1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the
2. When the Host controller is sending the ISO OUT data, because of system latencies,
3. While there is an underrun condition, if the Host controller is in the process of bit-stuff-
Problem Fix/Workaround
Problem Fix/Workaround
write and TD retirement write) to the system memory in order to complete the status
update.
transaction is completed, a frame boundary is crossed.
transaction.
system memory.
remaining bytes of the packet are not available. This results in a buffer underrun
condition.
ing, it causes the Host controller to hang.
6062M–ATARM–23-Mar-09