AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 584
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AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
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Figure 37-8. Data IN Transfer for Ping-pong Endpoint
584
TXPKTRDY Flag
(UDP_MCSRx)
FIFO (DPR)
Bank 0
FIFO (DPR)
USB Bus
Packets
TXCOMP Flag
(UDP_CSRx)
Bank 1
AT91SAM9261 Preliminary
Written by
Microcontroller
Microcontroller
Load Data IN Bank 0
Set by Firmware,
Data Payload Written in FIFO Bank 0
Warning: There is software critical path due to the fact that once the second bank is filled, the
driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP
is set and TX_PKTRDY is set too long, some Data IN packets may be NACKed, reducing the
bandwidth.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to
2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing
3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the
4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second
5. The microcontroller is notified that the first Bank has been released by the USB device
6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB
7. At this step, Bank 0 is available and the microcontroller can prepare a third data pay-
Data IN
PID
be cleared in the endpoint’s UDP_CSRx register.
zero or more byte values in the endpoint’s UDP_FDRx register.
FIFO by setting the TXPKTRDY in the endpoint’s UDP_CSRx register.
data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the
endpoint’s UDP_FDRx register.
when TXCOMP in the endpoint’s UDP_CSRx register is set. An interrupt is pending
while TXCOMP is being set.
device that it has prepared the second Bank to be sent, raising TXPKTRDY in the end-
point’s UDP_CSRx register.
load to be sent
Microcontroller Load Data IN Bank 1
USB Device Send Bank 0
Written by
Microcontroller
Read by USB Device
Data IN
Cleared by USB Device,
Data Payload Fully Transmitted
.
Set by USB
Device
ACK
PID
Interrupt Cleared by Firmware
Data IN
PID
Microcontroller Load Data IN Bank 0
USB Device Send Bank 1
Interrupt Pending
Written by
Microcontroller
Set by Firmware,
Data Payload Written in FIFO Bank 1
Read by USB Device
Data IN
Set by USB Device
6062M–ATARM–23-Mar-09
ACK
PID
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