AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 723

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6062M–ATARM–23-Mar-09
Doc. Rev.
6062K
Date
27-Aug-08 Comments
New!!!
Address Offsets added to register tables in User Interface sections of the datasheet.
AIC:
Section 27.8.15 ”AIC Spurious Interrupt Vector
Section 27.6.3 ”Interrupt
Debug and Test:
Table 12-3, “AT91SAM9261 JTAG Boundary Scan Register”
Name A19.
GPBR:
Section 18. ”General Purpose Backup Register
LCDC:
Table 38-1, “I/O Lines
Section 38.5.1.3
mode. Updated definitions.
Table 38-4, “Big Endian Memory
Section 38.10.23 ”Power Control
“pin” to “signal”.
Section 38.10.1 ”DMA Base Address Register
Section 38.5.2.7
Section 38.9.2 ”TFT Mode
”Horizontal Front Porch (HFP): The delay between end of valid data and the end of the line is
configurable in the HFP field of the LCDTIM2 register. The delay is equal to (HFP+2) LCDDOTCK
cycles.” on page
HFP+2 (not HFP+1) idem for
Section 38.10.12 ”LCD Timing Configuration Register 2”
and the timing diagrams
Figure 38-3 ”STN Panel Timing, CLKMOD 0”
Figure 38-4 ”TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1”
Figure 38-5 ”TFT Panel Timing (Line Expanded View), CLKMOD=1”
PMC:
Section 25.1 ”Overview”
Section 25.3 ”Processor Clock
Figure 24-1 ”Typical Slow Clock Crystal Oscillator
Section 25.7 ”Programming
to 0...”
Section 27.7.5 ”Protect
”Channel-U”, Removed equations for STN Monochrome mode and STN Color
”Shifter”, fixed typo: “LDCCON3 register” corrected to read “LCDCON2 register”
624.
Description”, updated description of LCDDEN.
Mode”, enabling Debug Control Protect Mode in AIC_DCR register updated. 5193
• PCK must be switched off when entering processor in Idle Mode.
Sources”, Interupt Source 1 OR-wiring description updated .
Example”, HFP = (16-2), HBP = (48 -1), HPW = (64-1), typo corrected.
Sequence”, correction to
Controller”, updated with information on “Wait for Interrup Mode”.
Organization”, Inverted Pixel 1bpp row values to go from 0 to 31.
Register”, LCD_PWR bit description, changed all occurences of
1”, updated with new values for bits 0 and 1.
Register”, fixed typo in bitfields.
(GPBR)”, added to the datasheet
Connection”, GNDPLL changed to GNDBU.
Step
AT91SAM9261 Preliminary
5, and
Bit number 481 is assigned to Pin
Step
6, “....PRES parameter is set
Change
Request
Ref.
rfo
4749
5191
5530
5764
3587
4268
4488
4739
5619
rfo
4322
4470
5596
723