PIC16C782/JW Microchip Technology, PIC16C782/JW Datasheet - Page 25

• Manufacturer Part Number: PIC16C782/JW
• Description: IC MCU EPROM 2KX14 COMP 20CDIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C782/JW

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: EPROM, UV
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-CDIP (0.300", 7.62mm) Window
• For Use With: DVA16XP202 - ADAPTER DEVICE PIC16C781/782DM163012 - BOARD DEMO PICDEM FOR 16C781/782AC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Connectivity: -
• Other names: Q1137459

2.9
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13-bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or writable. All updates
to the PCH register occur through the PCLATH register.
2.9.1
PIC16C781/782 devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11 bits of
address to allow branching within any 2K program
memory page. When performing a CALL or GOTO
instruction, the upper 2 bits of the address are provided
by PCLATH<4:3>. When performing a CALL or GOTO
instruction, the user must ensure that the page select
bits are programmed so that the desired program mem-
ory page is addressed. A return instruction pops a PC
address off the stack onto the PC register. Therefore,
manipulation of the PCLATH<4:3> bits is not required
for the return instructions (which POPs the address
from the stack).
2.10
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Mid-range devices have an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW, or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
2001 Microchip Technology Inc.
PCL and PCLATH
Stack
PROGRAM MEMORY PAGING
Preliminary
2.11
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
known as indirect addressing.
Reading INDF itself, indirectly (FSR = 0), produces
00h. Writing to the INDF register indirectly results in a
no operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
EXAMPLE 2-1:
NEXT
CONTINUE
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-5.
FIGURE 2-4:
12
12 1110
PCH
PCH
2
INDF
PCLATH<4:3>
PCLATH<4:0>
5
PCLATH
PCLATH
movlw
movwf
clrf
incf
btfss
goto
:
PIC16C781/782
8 7
8 7
0x20
FSR
INDF
FSR
FSR,4 ;all done?
NEXT
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
LOADING OF PC IN
DIFFERENT SITUATIONS
PCL
;initialize pointer
;
;clear INDF register
;inc pointer
;NO, clear next
;YES, continue
PCL
to RAM
11
8
Opcode <10:0>
ALU
DS41171A-page 23
0
0
Instruction with
PCL as
Destination
GOTO, CALL