UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 963

• Manufacturer Part Number: UPD78F0533AGB-GAH-AX
• Description: MCU 8BIT 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0533AGB-GAH-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 55
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Serial
interface
CSIA0
Function
ADTP0: Automatic
data transfer address
point specification
register 0
ADTI0: Automatic
data transfer interval
specification register
0
3-wire serial I/O mode Take relationship with the other party of communication when setting the port mode
1-byte transmission/
reception
Communication start
3-wire serial I/O mode
with automatic
transmit/receive
function
Automatic
transmission/
reception mode
Automatic
transmission
Repeat transmission
mode
Details of Function
Be sure to clear bits 7 to 5 to “0”.
Because the setting of bit 5 (STBE0) and bit 4 (BUSYE0) of serial status register 0
(CSIS0) takes priority over the ADTI0 setting, the interval time based on the setting
of STBE0 and BUSYE0 is generated even when ADTI0 is cleared to 00H.
register and port register.
The SOA0 pin becomes low level by an SIOA0 write.
If CSIAE0 is set to 1 after data is written to SIOA0, communication does not start.
A wait state may be generated when data is written to the buffer RAM. For details,
see CHAPTER 36 CAUTIONS FOR WAIT.
Take the relationship with the other communicating party into consideration when
setting the port mode register and port register.
Because, in the automatic transmission/reception mode, the automatic
transmit/receive function writes/reads data to/from the internal buffer RAM after 1-
byte transmission/reception, an interval is inserted until the next
transmission/reception. As the buffer RAM write/read is performed at the same time
as CPU processing, the interval is dependent upon the value of automatic data
transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4
(STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic
transmit/receive interval time).
If an access to the buffer RAM by the CPU conflicts with an access to the buffer
RAM by serial interface CSIA0 during the interval period, the interval time specified
by automatic data transfer interval specification register 0 (ADTI0) may be extended.
Because, in the automatic transmission mode, the automatic transmit/receive
function reads data from the internal buffer RAM after 1-byte transmission, an
interval is inserted until the next transmission. As the buffer RAM read is performed
at the same time as CPU processing, the interval is dependent upon the value of
automatic data transfer interval specification register 0 (ADTI0) and the set values of
bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5)
Automatic transmit/receive interval time).
If an access to the buffer RAM by the CPU conflicts with an access to the buffer
RAM by serial interface CSIA0 during the interval period, the interval time specified
by automatic data transfer interval specification register 0 (ADTI0) may be extended.
Because, in the repeat transmission mode, a read is performed on the buffer RAM
after the transmission of one byte, the interval is included in the period up to the
next transmission. As the buffer RAM read is performed at the same time as CPU
processing, the interval is dependent upon automatic data transfer interval
specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0,
BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive
interval time).
If an access to the buffer RAM by the CPU conflicts with an access to the buffer
RAM by serial interface CSIA0 during the interval period, the interval time specified
by automatic data transfer interval specification register 0 (ADTI0) may be extended.
Cautions
APPENDIX D LIST OF CAUTIONS
p. 521
p. 522
p. 525
p. 527
p. 529
p. 530
p. 532
p. 534
p. 534
p. 539
p. 539
p. 541
p. 541
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