UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 139
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
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Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
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78K0/Kx2
3.3.4 Register addressing
3.4 Operand Address Addressing
instruction execution.
3.4.1 Implied addressing
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
[Function]
[Illustration]
The following methods are available to specify the register and memory (addressing) to undergo manipulation during
[Function]
[Operand format]
[Description example]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and
branched.
This function is carried out when the BR AX instruction is executed.
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the 78K0/Kx2 microcontroller instruction words, the following instructions employ implied addressing.
Because implied addressing can be automatically determined with an instruction, no particular operand format is
necessary.
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of the A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
MULU
DIVUW
ADJBA/ADJBS
ROR4/ROL4
Instruction
A register for multiplicand and AX register for product storage
AX register for dividend and quotient storage
A register for storage of numeric values that become decimal correction targets
A register for storage of digit data that undergoes digit rotation
rp
PC
7
15
A
Register to Be Specified by Implied Addressing
0
8
7
7
X
CHAPTER 3 CPU ARCHITECTURE
0
0
139
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