UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 503
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
UPD78F0533AGB-GAH-AX
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Quantity:
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Company:
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UPD78F0533AGB-GAH-AX
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78K0/Kx2
(2) Communication operation
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or
received in synchronization with the serial clock.
Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1.
Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n). In addition, data
can be received when bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0.
Reception is started when data is read from serial I/O shift register 1n (SIO1n).
However, communication is performed as follows if bit 5 (SSE11) of CSIM11 is 1 when serial interface CSI11 is in the
slave mode.
<1> Low level input to the SSI11 pin
<2> High level input to the SSI11 pin
<3> Data is written to SOTB11 or data is read from SIO11 while a high level is input to the SSI11 pin, then a low
<4> A high level is input to the SSI11 pin during transmission/reception or reception
After communication has been started, bit 0 (CSOT1n) of CSIM1n is set to 1. When communication of 8-bit data has
been completed, a communication completion interrupt request flag (CSIIF1n) is set, and CSOT1n is cleared to 0.
Then the next communication is enabled.
Cautions 1. Do not access the control register and data register when CSOT1n = 1 (during serial
Remark n = 0:
→ Transmission/reception is started when SOTB11 is written, or reception is started when SIO11 is read.
→ Transmission/reception or reception is held, therefore, even if SOTB11 is written or SIO11 is read,
level is input to the SSI11 pin
→ Transmission/reception or reception is started.
→ Transmission/reception or reception is suspended.
transmission/reception or reception will not be started.
2. When using serial interface CSI11, wait for the duration of at least one clock before the clock
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
communication).
operation is started to change the level of the SSI11 pin in the slave mode; otherwise,
malfunctioning may occur.
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
78K0/KD2 products
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
503
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