UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 341
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
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Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
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78K0/Kx2
(4) Timing of holding data by capture register
(5) Setting valid edge
(6) Re-triggering one-shot pulse
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(a) When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while
(b) The values of CR00n and CR01n are not guaranteed after 16-bit timer/event counter 0n stops.
Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3 and TMC0n2 = 00). Set the valid
edge by using ES0n0 and ES0n1.
Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode.
Be sure to input the next trigger after the current active level is output.
Remark n = 0:
CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not
guaranteed. At this time, an interrupt signal (INTTM00n/INTTM01n) is generated when the valid edge of the
TI00n/TI01n pin is detected (the interrupt signal is not generated when the reverse-phase edge of the TI00n pin is
detected).
When the count value is captured because the valid edge of the TI00n/TI01n pin was detected, read the value of
CR00n/CR01n after INTTM00n/INTTM01n is generated.
Value captured to CR01n
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
Capture read signal
TM0n count value
Count pulse
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
78K0/KD2 products
Edge input
INTTM01n
Figure 7-61. Timing of Holding Data by Capture Register
X
Capture operation
N
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
N + 1
N + 2
N + 1
M
Capture operation is performed
but read value is not guaranteed.
M + 1
M + 2
341
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