UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 534
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
460
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
SCKA0
ACSIIF
SOA0
TSF0
SIA0
Cautions 1. Because, in the automatic transmission/reception mode, the automatic transmit/receive
Remark
Figure 17-13. Example of Automatic Transmission/Reception Mode Operation Timings
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACSIIF: Interrupt request flag
TSF0:
2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by
function
transmission/reception, an interval is inserted until the next transmission/reception. As
the buffer RAM write/read is performed at the same time as CPU processing, the interval
is dependent upon the value of automatic data transfer interval specification register 0
(ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0
(CSIS0) (see (5) Automatic transmit/receive interval time).
serial interface CSIA0 during the interval period, the interval time specified by automatic
data transfer interval specification register 0 (ADTI0) may be extended.
Bit 0 of serial status register 0 (CSIS0)
writes/reads
Interval
data
to/from
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CHAPTER 17 SERIAL INTERFACE CSIA0
the
internal
buffer
RAM
after
1-byte
534
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