UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 561
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(2) IIC status register 0 (IICS0)
Address: FFAAH
Condition for clearing (MSTS0 = 0)
• When a stop condition is detected
• When ALD0 = 1 (arbitration loss)
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (ALD0 = 0)
• Automatically cleared after IICS0 register is read
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Symbol
This register indicates the status of I
IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period.
Reset signal generation clears IICS0 to 00H.
Caution If data is read from IICS0 register, a wait cycle is generated. Do not read data from IICS0 register
MSTS0
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other than
Remark
IICS0
ALD0
Condition for clearing (EXC0 = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
EXC0
0
1
0
1
0
1
IICS0 register. Therefore, when using the ALD0 bit, read the data of this bit before the data of the other bits.
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. MSTS0 bit is cleared.
when the peripheral hardware clock (f
FOR WAIT.
MSTS0
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
Extension code was not received.
Extension code was received.
<7>
Bit 7 of IIC control register 0 (IICC0)
After reset: 00H
ALD0
<6>
Figure 18-6. Format of IIC Status Register 0 (IICS0) (1/3)
EXC0
<5>
2
C.
R
Detection of extension code reception
Note
COI0
<4>
Detection of arbitration loss
Master device status
PRS
Condition for setting (MSTS0 = 1)
• When a start condition is generated
Condition for setting (ALD0 = 1)
• When the arbitration result is a “loss”.
) is stopped. For details, see CHAPTER 36 CAUTIONS
Condition for setting (EXC0 = 1)
• When the higher four bits of the received address data is
TRC0
<3>
either “0000” or “1111” (set at the rising edge of the
eighth clock).
ACKD0
CHAPTER 18 SERIAL INTERFACE IIC0
<2>
STD0
<1>
SPD0
<0>
561
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