UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 223
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
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Company:
Part Number:
UPD78F0533AGB-GAH-AX
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Quantity:
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
P30 to P32
P33
P60
P61
P62
P70 to P77
P120
P121
P122
P123
P124
P140
P141
P142
P143
P144
P145
Note
Remarks 1. ×:
Pin Name
Table 5-6. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2)
When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem
clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock
(EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the
clock operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock operation mode select register
(OSCCTL) and (3) Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H
(all of the P121 to P124 are I/O port pins). At this time, setting of PM121 to PM124 and P121 to P124 is not
necessary.
2. X1, X2, P31, and P32 of the product with an on-chip debug function (
INTP1 to INTP3
INTP4
TI51
TO51
SCL0
SDA0
EXSCL0
KR0 to KR7
INTP0
EXLVI
X1
X2
EXCLK
XT1
XT2
EXCLKS
PCL
INTP6
BUZ
INTP7
BUSY0
SCKA0
SIA0
SOA0
STB0
PM××: Port mode register
P××:
be used as on-chip debug mode setting pins (OCD0A, OCD0B, OCD1A, and OCD1B) when the on-chip
debug function is used. For how to connect an on-chip debug emulator (QB-MINI2), see CHAPTER 28
ON-CHIP DEBUG FUNCTION (
Note
Note
Note
Note
Note
Note
Don’t care
Port output latch
Function Name
Alternate Function
μ
PD78F05xxD AND 78F05xxDA ONLY).
Input
Input
Input
Output
I/O
I/O
Input
Input
Input
Input
Input
Input
Output
Input
Output
Input
Input
Input
Output
Input
Output
Output
I/O
−
−
−
−
CHAPTER 5 PORT FUNCTIONS
μ
PD78F05xxD and 78F05xxDA) can
PM××
1
1
1
0
0
1
1
1
1
×
×
×
×
×
×
0
1
0
1
1
1
0
1
0
0
0
P××
×
×
×
0
0
0
×
×
×
×
×
×
×
×
×
×
0
×
0
×
×
×
1
×
0
0
223
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