UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 614
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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UPD78F0533AGB-GAH-AX
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78K0/Kx2
18.6 Timing Charts
devices as its communication partner.
which specifies the data transfer direction, and then starts serial communication with the slave device.
data is transferred to the SO0 latch and is output (MSB first) via the SDA0 pin.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
When using the I
After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)),
Figures 18-27 and 18-28 show timing charts of the data communication.
IIC shift register 0 (IIC0)’s shift operation is synchronized with the falling edge of the serial clock (SCL0). The transmit
Data input via the SDA0 pin is captured into IIC0 at the rising edge of SCL0.
2
C bus mode, the master device outputs an address via the serial bus to select one of several slave
CHAPTER 18 SERIAL INTERFACE IIC0
614
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