UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 846
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
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Company:
Part Number:
UPD78F0533AGB-GAH-AX
Manufacturer:
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Quantity:
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78K0/Kx2
Caution The pins mounted depend on the product. Refer to Caution at the beginning of this chapter.
(2) Serial interface
Notes 1.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
SCL0 clock frequency
Setup time of restart condition
Hold time
Hold time when SCL0 = “L”
Hold time when SCL0 = “H”
Data setup time (reception)
Data hold time (transmission)
Setup time of stop condition
Bus free time
Transfer rate
Transfer rate
(T
(a) UART6 (dedicated baud rate generator output)
(b) UART0 (dedicated baud rate generator output)
(c) IIC0
A
2.
3.
4.
5.
= −40 to +110°C, 2.7 V ≤ V
Note 1
Parameter
Parameter
Parameter
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of t
(acknowledge) timing.
f
When f
When f
W
indicates the IIC0 transfer clock selected by the IICCL and IICX0 registers.
W
W
≥ 4.4 MHz is selected
< 4.4 MHz is selected
Note 2
f
t
t
t
t
t
t
t
t
Symbol
SCL
SU: STA
HD: STA
LOW
HIGH
SU: DAT
HD: DAT
SU: STO
BUF
DD
Symbol
Symbol
CHAPTER 32 ELECTRICAL SPECIFICATIONS (A2) GRADE PRODUCTS
= EV
Internal clock operation
EXSCL0 clock (6.4 MHz)
operation
f
selected
f
DD
W
W
= f
= f
≤ 5.5 V, AV
HD:DAT
XH
RH
/2
/2
Note 3
N
N
or f
selected
is during normal transfer and a wait state is inserted in the ACK
Conditions
W
Conditions
Conditions
= f
REF
EXSCL0
Note 3
≤ V
DD
, V
SS
= EV
Standard Mode
MIN.
250
4.7
4.0
4.7
4.7
4.0
4.0
4.7
SS
0
0
0
MIN.
MIN.
= AV
MAX.
SS
3.45
3.45
100
−
−
−
−
−
−
−
−
= 0 V)
TYP.
TYP.
High-Speed Mode
MIN.
1.25
100
0.6
0.6
1.3
0.6
0.6
1.3
0
0
0
MAX.
MAX.
625
625
1.00
0.9
MAX.
1.05
400
−
−
−
−
−
−
−
−
Note 4
Note 5
kbps
kbps
Unit
Unit
Unit
kHz
μ
μ
μ
μ
μ
ns
μ
μ
μ
μ
s
s
s
s
s
s
s
s
s
846
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