UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 571
UPD78F0533AGB-GAH-AX
Manufacturer Part Number
UPD78F0533AGB-GAH-AX
Description
MCU 8BIT 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0533AGB-GAH-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0/Kx2
18.5.2 Addresses
master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
matches the data values stored in slave address register 0 (SVA0). If the address data matches the SVA0 register values,
the slave device is selected and communicates with the master device until the master device generates a start condition
or stop condition.
specification below, are together written to IIC shift register 0 (IIC0) and are then output. Received addresses are written
to IIC0.
18.5.3 Transfer direction specification
a slave device. When the transfer direction specification bit has a value of “1”, it indicates that the master device is
receiving data from a slave device.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
The slave address and the eighth bit, which specifies the transfer direction as described in 18.5.3 Transfer direction
The slave address is assigned to the higher 7 bits of IIC0 register.
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting data to
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
operation.
INTIIC0
INTIIC0
SDA0
SCL0
SDA0
SCL0
Figure 18-15. Transfer Direction Specification
A6
A6
1
1
A5
A5
2
2
Figure 18-14. Address
A4
A4
3
3
Address
A3
A3
4
4
A2
A2
5
5
A1
Transfer direction specification
A1
6
6
CHAPTER 18 SERIAL INTERFACE IIC0
A0
A0
7
7
R/W
R/W
8
8
9
9
Note
Note
571
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