DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 559

• Manufacturer Part Number: DF3048X16V
• Description: MCU 5V 128K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048X16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6) After transmitting one frame, if the receiving device returns an error signal, the SCI sets the
(7) The TEND bit in SSR is not set for the frame in which the error signal was received, indicating
(8) If no error signal is returned from the receiving device, the ERS flag is not set in SSR.
(9) If no error signal is returned from the receiving device, transmission of the frame, including
TEND
ERS
Retransmission when SCI is in Transmit Mode (see figure 14.12)
ERS flag to 1 in SSR. If the RIE bit in SCR is set to the enable state, an ERI interrupt is
requested. The ERS flag should be cleared to 0 in SSR before the next parity bit sampling
timing.
an error.
retransmission, is assumed to be complete, and the TEND bit is set to 1 in SSR. If the TIE bit
in SCR is set to the enable state, a TXI interrupt is requested. If TXI is enabled as a DMA
transfer activation source, the next data can be written in TDR automatically. When the
DMAC writes data in TDR, it automatically clears the TDRE bit to 0.
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
TDRE
Transfer from TDR to TSR
Frame n
Figure 14.12 Retransmission in SCI Transmit Mode
DE
(6)
(7)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer from TDR to TSR
Retransmitted frame
Rev. 7.00 Sep 21, 2005 page 533 of 878
Section 14 Smart Card Interface
(DE)
(8)
(9)
Ds
Transfer from
TDR to TSR
REJ09B0259-0700
D0 D1 D2 D3 D4
Frame n + 1