DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 360
![MCU 5V 128K,PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048X16V
Manufacturer Part Number
DF3048X16V
Description
MCU 5V 128K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048X16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048X16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 360 of 907
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Section 10 16-Bit Integrated Timer Unit (ITU)
Before selecting reset-synchronized PWM mode or complementary PWM mode, halt the timer
counter or counters that will be used in these modes.
When these bits select complementary PWM mode or reset-synchronized PWM mode, they take
precedence over the setting of the PWM mode bits (PWM4 and PWM3) in TMDR. Settings of
complementary PWM mode or reset-synchronized PWM mode and settings of timer sync bits
SYNC4 and SYNC3 in TSNC are valid simultaneously, however, when complementary PWM
mode is selected, channels 3 and 4 must not be synchronized (do not set bits SYNC3 and SYNC4
both to 1 in TSNC).
Bit 3—Buffer Mode B4 (BFB4): Selects whether GRB4 operates normally in channel 4, or
whether GRB4 is buffered by BRB4.
Bit 2—Buffer Mode A4 (BFA4): Selects whether GRA4 operates normally in channel 4, or
whether GRA4 is buffered by BRA4.
Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or
whether GRB3 is buffered by BRB3.
Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or
whether GRA3 is buffered by BRA3.
Rev. 7.00 Sep 21, 2005 page 334 of 878
REJ09B0259-0700
Bit 3: BFB4
0
1
Bit 2: BFA4
0
1
Bit 1: BFB3
0
1
Bit 0: BFA3
0
1
Description
GRB4 operates normally
GRB4 is buffered by BRB4
Description
GRA4 operates normally
GRA4 is buffered by BRA4
Description
GRB3 operates normally
GRB3 is buffered by BRB3
Description
GRA3 operates normally
GRA3 is buffered by BRA3
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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