DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 189
![MCU 5V 128K,PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048X16V
Manufacturer Part Number
DF3048X16V
Description
MCU 5V 128K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048X16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048X16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 189 of 907
- Download datasheet (6Mb)
Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh
during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set
to 1, pseudo-static RAM can be self-refreshed when the H8/3048 Group enters software standby
mode. When PSRAME = 0 and DRAME = 1, after the SRFMD bit is set to 1, DRAM can be self-
refreshed when the H8/3048 Group enters software standby mode. In either case, the normal
access state resumes on exit from software standby mode.
Bit 6—PSRAM Enable (PSRAME) and
Bit 5—DRAM Enable (DRAME): These bits enable or disable connection of pseudo-static RAM
and DRAM to area 3 of the external address space.
When DRAM or pseudo-static RAM is connected, the bus cycle and refresh cycle of area 3 consist
of three states, regardless of the setting in the access state control register (ASTCR). If AST3 = 0
in ASTCR, wait states cannot be inserted.
When the PSRAME or DRAME bit is set to 1, bits 0, 2, 3, and 4 in RFSHCR and registers
RTMCSR, RTCNT, and RTCOR are write-disabled, except that the CMF flag in RTMCSR can be
cleared by writing 0.
Bit 4—Strobe Mode Select (CAS/WE
valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or
DRAME bit is set to 1.
Bit 7: SRFMD
0
1
Bit 6: PSRAME
0
1
Bit 4: CAS/WE
0
1
WE
WE
WE
Description
DRAM or PSRAM self-refresh is disabled in software standby mode
DRAM or PSRAM self-refresh is enabled in software standby mode
Bit 5: DRAME
0
1
0
1
Description
2WE mode
2CAS mode
WE): Selects 2CAS or 2WE mode. The setting of this bit is
WE
WE
Description
Can be used as an interval timer
(DRAM and PSRAM cannot be directly connected)
DRAM can be directly connected
PSRAM can be directly connected
Illegal setting
Rev. 7.00 Sep 21, 2005 page 163 of 878
Section 7 Refresh Controller
REJ09B0259-0700
(Initial value)
(Initial value)
(Initial value)
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