DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 468
![MCU 5V 128K,PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3048X16V
Manufacturer Part Number
DF3048X16V
Description
MCU 5V 128K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048X16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048X16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 468 of 907
- Download datasheet (6Mb)
Section 12 Watchdog Timer
12.2.3
RSTCSR is an 8-bit readable and writable * register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Note: * RSTCSR differs from other registers in being more difficult to write. For details see
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices.
Rev. 7.00 Sep 21, 2005 page 442 of 878
REJ09B0259-0700
Bit 7: WRST
0
1
Bit
Initial value
Read/Write
Note: * Only 0 can be written in bit 7, to clear the flag.
section 12.2.4, Notes on Register Access.
Reset Control/Status Register (RSTCSR)
Watchdog timer reset
Indicates that a reset signal has been generated
R/(W)
WRST
Description
[Clearing conditions]
Cleared to 0 by reset signal input at RES pin
Cleared by reading WRST when WRST = 1, then writing 0 in WRST
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer
operation
7
0
*
Reset output enable
Enables or disables external output of the reset signal
RSTOE
R/W
6
0
—
—
5
1
—
—
4
1
Reserved bits
—
—
3
1
—
—
2
1
—
—
1
1
(Initial value)
—
—
0
1
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