DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 398

• Manufacturer Part Number: DF3048X16V
• Description: MCU 5V 128K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048X16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Integrated Timer Unit (ITU)
Setup Procedure for Complementary PWM Mode: Figure 10.33 shows a sample procedure for
setting up complementary PWM mode.
Rev. 7.00 Sep 21, 2005 page 372 of 878
REJ09B0259-0700
Note: After exiting complementary PWM mode, to resume operating in complementary
Figure 10.33 Setup Procedure for Complementary PWM Mode (Example)
PWM mode, follow the entire setup procedure from step 1 again.
Complementary PWM mode
Complementary PWM mode
Select complementary
Set general registers
Select counter clock
Start counters
Stop counting
PWM mode
Set TCNTs
1
2
3
4
5
6
1. Clear bits STR3 and STR4 to 0 in
2. Set bits TPSC2 to TPSC0 in TCR to
3. Set bits CMD1 and CMD0 in TFCR
4. Clear TCNT4 to H'0000. Set the
5. GRA3 is the waveform period
6. Set bits STR3 and STR4 in TSTR to
TSTR to halt the timer counters.
Complementary PWM mode must be
set up while TCNT3 and TCNT4 are
halted.
select the same counter clock source
for channels 3 and 4. If an external
clock source is selected, select the
external clock edge(s) with bits
CKEG1 and CKEG0 in TCR. Do not
select any counter clear source
with bits CCLR1 and CCLR0 in TCR.
to select complementary PWM mode.
TIOCA
TOCXA
become PWM output pins.
non-overlap margin in TCNT3. Do not
set TCNT3 and TCNT4 to the same
value.
register. Set the upper limit value of
TCNT3 minus 1 in GRA3. Set
transition times of the PWM output
waveforms in GRB3, GRA4, and
GRB4. Set times within the compare
match range of TCNT3 and TCNT4.
T
GRA4, or GRB4. T: initial setting of
TCNT3)
1 to start TCNT3 and TCNT4.
X (X: initial setting of GRB3,
3
, TIOCB
4
, and TOCXB
3
, TIOCA
4
automatically
4
, TIOCB
4
,