DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 967
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4. FKEY is cleared to H'00 for protection.
5. The value of the DPFR parameter must be checked and the download result must be
⎯ The user-MAT space is switched to the on-chip program storage area.
⎯ After the selection condition of the download program and the FTDAR setting are checked,
⎯ The SCO bits in FPCS, FECS, and FCCS are cleared to 0.
⎯ The return value is set to the DPFR parameter.
⎯ After the on-chip program storage area is returned to the user-MAT space, the user
The notes on download are as follows.
⎯ In the download processing, the values of general registers of the CPU are held.
⎯ In the download processing, any interrupts are not accepted. However, interrupt requests
⎯ The sources of the interrupt requests from the on-chip module and at the falling edge of the
⎯ When the level-detection interrupt requests are to be held, interrupts must be input until the
⎯ When hardware standby mode is entered during download processing, the normal
⎯ Since a stack area of a maximum 128-byte is used, the area must be allocated before setting
⎯ If a flash memory access by the DMAC, DTC, or BREQ signal is requested during
confirmed.
⎯ Check the value of the DPFR parameter (one byte of start address of the download
⎯ If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the
the transfer processing to the on-chip RAM specified by FTDAR is executed.
procedure program is returned.
other than the NMI are held. Therefore, when the user procedure program is returned, the
NMI interrupts occur. NMI requests are discarded if the FVACR value is H'00. However, if
H'88 has been written to FVACR, they are held and the interrupts are generated when
processing returns to the user procedure program.
IRQ are held during downloading. The refresh cycles for the DRAM can be inserted.
download is ended.
download cannot be guaranteed in the on-chip RAM. Therefore, download must be
executed again.
the SCO bit to 1.
downloading, the operation cannot be guaranteed. Therefore, an access request by the
DMAC, DTC, or BREQ signal must not be generated.
destination specified by FTDAR). If the value is H'00, download has been performed
normally. If the value is not H'00, the source that caused download to fail can be
investigated by the description below.
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
Section 21 Flash Memory (0.18-μm F-ZTAT Version)
Rev.7.00 Mar. 18, 2009 page 899 of 1136
REJ09B0109-0700
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