DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 52
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 52 of 1208
- Download datasheet (8Mb)
Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode
Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode
Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode
Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode
Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode
Figure 8.45 Transfer End Interrupt Logic................................................................................... 420
Figure 8.46 Example of Procedure for Restarting Transfer on Channel
Section 9 Data Transfer Controller (DTC) ........................................................ 425
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Figure 9.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ................... 444
Figure 9.11 DTC Operation Timing (Example of Block Transfer Mode,
Figure 9.12 DTC Operation Timing (Example of Chain Transfer) ............................................ 445
Figure 9.13 Chain Transfer when Counter = 0 ........................................................................... 451
Section 11 16-Bit Timer Pulse Unit (TPU) ....................................................... 545
Figure 11.1 Block Diagram of TPU............................................................................................ 548
Figure 11.2 Example of Counter Operation Setting Procedure .................................................. 583
Figure 11.3 Free-Running Counter Operation ............................................................................ 584
Figure 11.4 Periodic Counter Operation..................................................................................... 585
Figure 11.5 Example of Setting Procedure for Waveform Output by Compare Match.............. 586
Figure 11.6 Example of 0 Output/1 Output Operation ............................................................... 587
Figure 11.7 Example of Toggle Output Operation ..................................................................... 587
Figure 11.8 Example of Setting Procedure for Input Capture Operation.................................... 588
Figure 11.9 Example of Input Capture Operation ...................................................................... 589
Figure 11.10 Example of Synchronous Operation Setting Procedure .......................................... 590
Rev.7.00 Mar. 18, 2009 page l of lxvi
REJ09B0109-0700
(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) .............. 413
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0) ..................... 414
(CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1)........................ 415
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1) ..................... 416
(Contention with Another Channel/Dual Address Mode/Low Level Sensing) ....... 417
in which Transfer End Interrupt Occurred .............................................................. 421
Block Diagram of DTC ........................................................................................... 426
Block Diagram of DTC Activation Source Control ................................................ 433
Correspondence between DTC Vector Address and Register Information ............. 434
Correspondence between DTC Vector Address and Register Information ............. 434
Flowchart of DTC Operation .................................................................................. 438
Memory Mapping in Normal Mode ........................................................................ 440
Memory Mapping in Repeat Mode ......................................................................... 441
Memory Mapping in Block Transfer Mode ............................................................ 442
Operation of Chain Transfer.................................................................................... 443
with Block Size of 2)............................................................................................... 445
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