DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 30
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 30 of 1208
- Download datasheet (8Mb)
7.6
7.7
Section 8 EXDMA Controller (EXDMAC) ...................................................... 359
8.1
8.2
8.3
8.4
Rev.7.00 Mar. 18, 2009 page xxviii of lxvi
REJ09B0109-0700
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles.............................................. 340
7.5.11 Write Data Buffer Function .................................................................................. 346
7.5.12 Multi-Channel Operation ...................................................................................... 347
7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles,
7.5.14 DMAC and NMI Interrupts................................................................................... 350
7.5.15 Forced Termination of DMAC Operation............................................................. 351
7.5.16 Clearing Full Address Mode ................................................................................. 352
Interrupt Sources ................................................................................................................ 353
Usage Notes ....................................................................................................................... 354
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
Features .............................................................................................................................. 359
Input/Output Pins ............................................................................................................... 361
Register Descriptions ......................................................................................................... 362
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
Operation............................................................................................................................ 374
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
Idle Mode.............................................................................................................. 314
Repeat Mode ......................................................................................................... 316
Single Address Mode............................................................................................ 320
Normal Mode........................................................................................................ 323
Block Transfer Mode ............................................................................................ 326
Basic Bus Cycles................................................................................................... 331
DMA Transfer (Dual Address Mode) Bus Cycles ................................................ 332
and EXDMAC ...................................................................................................... 349
DMAC Register Access during Operation............................................................ 354
Module Stop.......................................................................................................... 355
Write Data Buffer Function .................................................................................. 356
TEND Output........................................................................................................ 356
Activation by Falling Edge on DREQ Pin ............................................................ 357
Activation Source Acceptance .............................................................................. 358
Internal Interrupt after End of Transfer................................................................. 358
Channel Re-Setting ............................................................................................... 358
EXDMA Source Address Register (EDSAR) ....................................................... 362
EXDMA Destination Address Register (EDDAR) ............................................... 362
EXDMA Transfer Count Register (EDTCR)........................................................ 363
EXDMA Mode Control Register (EDMDR) ........................................................ 365
EXDMA Address Control Register (EDACR) ..................................................... 370
Transfer Modes ..................................................................................................... 374
Address Modes ..................................................................................................... 375
DMA Transfer Requests ....................................................................................... 379
Bus Modes ............................................................................................................ 379
Transfer Modes ..................................................................................................... 381
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