DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 237
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 237 of 1208
- Download datasheet (8Mb)
Bit
5
4
3
2
1
0
Bit Name
RLW1
RLW0
SLFRF
TPCS2
TPCS1
TPCS0
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Refresh Cycle Wait Control
These bits select the number of wait states to be
inserted in a DRAM interface CAS-before-RAS
refresh cycle/synchronous DRAM interface auto-
refresh cycle. This setting applies to all areas
designated as DRAM/continuous synchronous
DRAM space.
00: No wait state inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
Self-Refresh Enable
If this bit is set to 1, DRAM/synchronous DRAM
self-refresh mode is selected when a transition is
made to the software standby state. This bit is valid
when the RFSHE bit is set to 1, enabling refresh
operations. It is cleared after recovery from
software standby mode.
0: Self-refreshing is disabled
1: Self-refreshing is enabled
Self-Refresh Precharge Cycle Control
These bits select the number of states in the
precharge cycle immediately after self-refreshing.
The number of states in the precharge cycle
immediately after self-refreshing are added to the
number of states set by bits TPC1 and TPC0 in
DRACCR.
000: [TPC set value] states
001: [TPC set value + 1] states
010: [TPC set value + 2] states
011: [TPC set value + 3] states
100: [TPC set value + 4] states
101: [TPC set value + 5] states
110: [TPC set value + 6] states
111: [TPC set value + 7] states
Rev.7.00 Mar. 18, 2009 page 169 of 1136
Section 6 Bus Controller (BSC)
REJ09B0109-0700
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