DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 777
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 777 of 1208
- Download datasheet (8Mb)
Bit
2
1
0
Note:
Bit Name
TEND
MPB
MPBT
1. Only 0 can be written, to clear the flag. Alternately, use the bit clear instruction to clear
2. Elementary time unit (etu): Transfer duration for one bit
the flag.
Initial Value
1
0
0
R/W
R
R
R/W
Section 15 Serial Communication Interface (SCI, IrDA)
Description
Transmit End
This bit is set to 1 when no error signal has been
sent back from the receiving end and the next
transmit data is ready to be transferred to TDR.
[Setting conditions]
•
•
Timing to set this bit differs according to the
register settings.
GM = 0, BLK = 0: 2.5 etu *
GM = 0, BLK = 1: 1.5 etu *
GM = 1, BLK = 0: 1.0 etu *
GM = 1, BLK = 1: 1.0 etu *
•
•
Multiprocessor Bit
This bit is not used in Smart Card interface mode.
Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
[Clearing conditions]
When the TE bit in SCR is 0 and the ERS bit is
also 0
If the ERS bit is 0 and the TDRE bit is 1 after
the specified interval after transmission of 1-
byte data
When 0 is written to TEND after reading TEND
= 1
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
Rev.7.00 Mar. 18, 2009 page 709 of 1136
2
2
2
2
after transmission
after transmission
after transmission
after transmission
REJ09B0109-0700
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