DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 53
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 53 of 1208
- Download datasheet (8Mb)
Figure 11.11 Example of Synchronous Operation........................................................................ 591
Figure 11.12 Compare Match Buffer Operation........................................................................... 592
Figure 11.13 Input Capture Buffer Operation............................................................................... 592
Figure 11.14 Example of Buffer Operation Setting Procedure..................................................... 593
Figure 11.15 Example of Buffer Operation (1) ............................................................................ 594
Figure 11.16 Example of Buffer Operation (2) ............................................................................ 595
Figure 11.17 Cascaded Operation Setting Procedure ................................................................... 596
Figure 11.18 Example of Cascaded Operation (1)........................................................................ 597
Figure 11.19 Example of Cascaded Operation (2)........................................................................ 597
Figure 11.20 Example of PWM Mode Setting Procedure ............................................................ 600
Figure 11.21 Example of PWM Mode Operation (1) ................................................................... 601
Figure 11.22 Example of PWM Mode Operation (2) ................................................................... 601
Figure 11.23 Example of PWM Mode Operation (3) ................................................................... 602
Figure 11.24 Example of Phase Counting Mode Setting Procedure............................................. 603
Figure 11.25 Example of Phase Counting Mode 1 Operation ...................................................... 604
Figure 11.26 Example of Phase Counting Mode 2 Operation ...................................................... 605
Figure 11.27 Example of Phase Counting Mode 3 Operation ...................................................... 606
Figure 11.28 Example of Phase Counting Mode 4 Operation ...................................................... 607
Figure 11.29 Phase Counting Mode Application Example........................................................... 609
Figure 11.30 Count Timing in Internal Clock Operation.............................................................. 612
Figure 11.31 Count Timing in External Clock Operation ............................................................ 612
Figure 11.32 Output Compare Output Timing ............................................................................. 613
Figure 11.33 Input Capture Input Signal Timing.......................................................................... 613
Figure 11.34 Counter Clear Timing (Compare Match) ................................................................ 614
Figure 11.35 Counter Clear Timing (Input Capture) .................................................................... 614
Figure 11.36 Buffer Operation Timing (Compare Match) ........................................................... 615
Figure 11.37 Buffer Operation Timing (Input Capture) ............................................................... 615
Figure 11.38 TGI Interrupt Timing (Compare Match) ................................................................. 616
Figure 11.39 TGI Interrupt Timing (Input Capture) ..................................................................... 616
Figure 11.40 TCIV Interrupt Setting Timing................................................................................ 617
Figure 11.41 TCIU Interrupt Setting Timing................................................................................ 617
Figure 11.42 Timing for Status Flag Clearing by CPU ................................................................ 618
Figure 11.43 Timing for Status Flag Clearing by DTC/DMAC Activation ................................. 618
Figure 11.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .................. 619
Figure 11.45 Contention between TCNT Write and Clear Operations......................................... 620
Figure 11.46 Contention between TCNT Write and Increment Operations ................................. 621
Figure 11.47 Contention between TGR Write and Compare Match ............................................ 622
Figure 11.48 Contention between Buffer Register Write and Compare Match............................ 623
Figure 11.49 Contention between TGR Read and Input Capture ................................................. 624
Figure 11.50 Contention between TGR Write and Input Capture ................................................ 625
Figure 11.51 Contention between Buffer Register Write and Input Capture................................ 626
Rev.7.00 Mar. 18, 2009 page li of lxvi
REJ09B0109-0700
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