DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 364
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 364 of 1208
- Download datasheet (8Mb)
Section 7 DMA Controller (DMAC)
Bit
3
2
1
0
Full Address Mode:
• DMABCRH
Bit
15
14
Rev.7.00 Mar. 18, 2009 page 296 of 1136
REJ09B0109-0700
Bit Name
DTIE1B
DTIE1A
DTIE0B
DTIE0A
Bit Name
FAE1
FAE0
Initial Value
0
0
0
0
Initial Value
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Data Transfer End Interrupt Enable 1B
Data Transfer End Interrupt Enable 1A
Data Transfer End Interrupt Enable 0B
Data Transfer End Interrupt Enable 0A
These bits enable or disable an interrupt to the
CPU or DTC when transfer ends. If the DTIE bit is
set to 1 when DTE = 0, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE bit to 0 in the interrupt handling
routine, or by performing processing to continue
transfer by setting the transfer counter and address
register again, and then setting the DTE bit to 1.
Description
Full Address Enable 1
Specifies whether channel 1 is to be used in short
address mode or full address mode.
In full address mode, channels 1A and 1B are used
together as channel 1.
0: Short address mode
1: Full address mode
Full Address Enable 0
Specifies whether channel 0 is to be used in short
address mode or full address mode.
In full address mode, channels 0A and 0B are used
together as channel 0.
0: Short address mode
1: Full address mode
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