DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 348
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 348 of 1208
- Download datasheet (8Mb)
Section 7 DMA Controller (DMAC)
A block diagram of the DMAC is shown in figure 7.1.
Rev.7.00 Mar. 18, 2009 page 280 of 1136
REJ09B0109-0700
Internal interrupts
External pins
Interrupt signals
Legend:
DMAWER : DMA write enable register
DMATCR : DMA terminal control register
DMABCR : DMA band control register (for all channels)
DMACR
MAR
IOAR
ETCR
DMTEND0A
DMTEND0B
DMTEND1A
DMTEND1B
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
TXI0
RXI0
TXI1
RXI1
ADI
DREQ0
DREQ1
TEND0
TEND1
DACK0
DACK1
: DMA control register
: Memory address register
: I/O address register
: Execute transfer count register
Data buffer
Control logic
Figure 7.1 Block Diagram of DMAC
DMABCR
DMAWER
DMATCR
DMACR0A
DMACR0B
DMACR1A
DMACR1B
Internal address bus
Internal data bus
MAR_0AH
MAR_0BH
MAR_1AH
MAR_1BH
Address buffer
Processor
ETCR_0A
ETCR_0B
ETCR_1A
ETCR_1B
IOAR_0A
IOAR_0B
IOAR_1A
IOAR_1B
MAR_0AL
MAR_0BL
MAR_1AL
MAR_1BL
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