DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 859
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 859 of 1208
- Download datasheet (8Mb)
(master output)
16.4.4
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
2. When the slave address matches in the first frame following detection of the start condition,
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
(master output)
(slave output)
processing
bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS in ICCRA and TDRE in ICSR
are set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by clearing TDRE after writing transmit data to ICDRT every time
TDRE is set.
with TDRE = 1. When TEND is set, clear TEND.
ICDRR
SCL
SDA
SDA
ICDRS
RDRF
RCVD
User
Slave Transmit Operation
Data n-1
A
9
[5] Read ICDRR and clear RDRF
Figure 16.8 Master Receive Mode Operation Timing 2
Data n-1
after setting RCVD.
Bit 7
1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
[7] Read ICDRR, clear RDRF,
5
and clear RCVD
Section 16 I
Bit 2
6
Rev.7.00 Mar. 18, 2009 page 791 of 1136
Bit 1
7
2
C Bus Interface 2 (IIC2) (Option)
Bit 0
Data n
8
A/A
9
Data n
[6] Issue stop
condition
REJ09B0109-0700
[8] Set slave
receive mode
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