MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 744

• Manufacturer Part Number: MCF5281CVM66J
• Description: IC MPU 256K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5281CVM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Revision History
B.7
B-8
Table 2-1/Page 2-4 Remove last sentence in C bit field description.
Table 2-3/Page 2-7 Change PC’s Written with MOVEC entry to “No”.
Table 4-3/Page 4-5 Change reset value of ACR0, ACR1 to “See Section” since some of the bits are undefined after reset.
Table 4-5/Page 4-8 For split instruction/data cache entry, swap text in parantheses in the description field. Instruction cache
Table 5-1/Page 5-2 The PRI1/PRI2 text description does not match the table below it. It should be: “If a bit is set, CPU has
Table 6-2/Page 6-7 Changed bit description of FLASHBAR[WP] to read-only and that this bit is always set.
Table 25-19/25-32 Changed BUFnI field description from “To clear an interrupt flag, first read the flag as a one, then write it
Section 2.5/Page
Section 2.5/Page
4.4.2.2/Page 4-9
Figure 3-6/Page
Figure 4-2/Page
Figure 4-3/Page
Figure 5-1/Page
Figure 6-3/Page
Throughout
Chapter 33
Location
Location
Preface
Section
2-8
2-9
3-8
4-6
4-9
5-2
6-6
Changes Between Rev. 2.3 and Rev. 3
Updated power consumption tables.
Added MCF5214 and MCF5216 to list of the devices supported in this document. These two devices are
Changed title of document.
Moved revision history to this appendix
Change last bullet to “Use of separate system stack pointers for user and supervisor modes”
Change last sentence in fourth paragraph (step 2) to “The IACK cycle is mapped to special locations
within the interrupt controller's address space with the interrupt level encoded in the address."
Add minus sign to the exponent so that it is “–(i + 1 – N)”.
Change CACR fields to R/W, since they may be read via the debug module.
uses the upper half of the arrays, while data cache uses the lower half.
Change reset value of ACR: Bits 31-16, 14-13, 6-5, and 2 are undefined, and other bits are cleared.
Change ACR fields to R/W, since they may be read via the debug module.
Change note to:
Change RAMBAR fields to R/W, since they may be read via the debug module.
Changed FLASHBAR[WP] to read-only.
as a zero” to “To clear an interrupt flag, first read the flag as a one, then write it as a one.”
the same as the MCF5282 except they do not have an FEC and have a rated frequency of 66 MHz.
priority. If a bit is cleared, DMA has priority.”
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table B-6. Rev. 2.2 to Rev. 2.3 Changes (continued)
Peripheral (IPSBAR) space should not be cached. The combination
of the CACR defaults and the two ACRn registers must define the
non-cacheable attribute for this address space.
Table B-7. Rev. 2.3 to Rev. 3 Changes
Description
Description
NOTE
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