MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 339
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MCF5281CVM66J
Manufacturer Part Number
MCF5281CVM66J
Description
IC MPU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5281CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5281CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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17.5.1.3
Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs.
The Ethernet controller confirms transmission by clearing the ready bit (TxBD[R]) when DMA of the
buffer is complete. In the TxBD, the user initializes the R, W, L, and TC bits and the length (in bytes) in
the first longword and the buffer pointer in the second longword.
The FEC clears the R bit when the buffer is transferred. Status bits for the buffer/frame are not included in
the transmit buffer descriptors. Transmit frame status is indicated via individual interrupt bits (error
conditions) and in statistic counters in the MIB block. See
Map,”
Freescale Semiconductor
1
Offset + 0
Offset + 0
Offset + 6
0ffset + 4
The receive buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 16. The
buffer must reside in memory external to the FEC. The Ethernet controller never modifies this value.
Word
Word
Offset + 0
Offset + 2
Offset + 4
Offset + 6
for more details.
Ethernet Transmit Buffer Descriptor (TxBD)
A[31:16]
Field
TO1
A[15:0]
15
R
15
14
Field
15–0
15–0
When the software driver sets an E bit in one or more receive descriptors,
the driver should follow with a write to RDAR.
R
TO1
Table 17-29. Receive Buffer Descriptor Field Definitions (continued)
14
Ready. Written by the FEC and you.
0 The data buffer associated with this BD is not ready for transmission. You are free to manipulate
1 The data buffer, prepared for transmission by you, has not been transmitted or currently transmits.
Transmit software ownership. This field is reserved for software use. This read/write bit is not modified
by hardware nor does its value affect hardware.
RX data buffer pointer, bits [31:16]
RX data buffer pointer, bits [15:0]
this BD or its associated data buffer. The FEC clears this bit after the buffer has been transmitted
or after an error condition is encountered.
You may write no fields of this BD after this bit is set.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 17-30. Transmit Buffer Descriptor Field Definitions
W
13
Figure 17-26. Transmit Buffer Descriptor (TxBD)
TO2
12
11
L
TC
10
Tx Data Buffer Pointer - A[31:16]
Tx Data Buffer Pointer - A[15:0]
ABC
9
NOTE
1
Data Length
—
8
Section 17.4.1, “MIB Block Counters Memory
Description
Description
—
7
—
6
—
5
—
4
Fast Ethernet Controller (FEC)
—
3
—
2
—
1
—
0
17-29
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