MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 340

• Manufacturer Part Number: MCF5281CVM66J
• Description: IC MPU 256K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5281CVM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
1
17.5.2
This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC,
and what locations you must initialize prior to enabling the FEC.
17.5.2.1
In the FEC, hardware resets registers and control logic that generate interrupts. A hardware reset negates
output signals and resets general configuration bits.
17-30
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 2
Offset + 4
Offset + 6
The transmit buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 4. The
buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
Word
Initialization Sequence
A[31:16]
Length
A[15:0]
Hardware Controlled Initialization
Field
15–0
15–0
15–0
ABC
Data
TO2
8–0
TC
13
12
11
10
W
After the software driver has set up the buffers for a frame, it should set up
the corresponding BDs. The last step in setting up the BDs for a transmit
frame is setting the R bit in the first BD for the frame. The driver must
follow that with a write to TDAR that triggers the FEC to poll the next BD
in the ring.
L
9
Table 17-30. Transmit Buffer Descriptor Field Definitions (continued)
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ETDSR.
Transmit software ownership. This field is reserved for use by software. This read/write bit is not
modified by hardware nor does its value affect hardware.
Last in frame. Written by user.
0 The buffer is not the last in the transmit frame
1 The buffer is the last in the transmit frame
Transmit CRC. Written by user (only valid if L is set).
0 End transmission immediately after the last data byte
1 Transmit the CRC sequence after the last data byte
Append bad CRC. Written by user (only valid if L is set).
0 No effect
1 Transmit the CRC sequence inverted after the last data byte (regardless of TC value)
Reserved, must be cleared.
Data length, written by user.
Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never
modified by the FEC.
Tx data buffer pointer, bits [31:16]
Tx data buffer pointer, bits [15:0]
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
NOTE
1
Description
Freescale Semiconductor