MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 323
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MCF5281CVM66J
Manufacturer Part Number
MCF5281CVM66J
Description
IC MPU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5281CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5281CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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17.4.7
The MMFR is user-accessible and does not reset to a defined value. The MMFR register is used to
communicate with the attached MII compatible PHY device(s), providing read/write access to their MII
registers. Performing a write to the MMFR causes a management frame to be sourced unless the MSCR is
programmed to 0. If MSCR is cleared while MMFR is written and then MSCR is written with a non-zero
value, an MII frame is generated with the data previously written to the MMFR. This allows MMFR and
MSCR to be programmed in either order if MSCR is currently zero.
Freescale Semiconductor
ETHER_EN
IPSBAR
RESET
Offset:
Field
31–2
Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
0
IPSBAR
W
R 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETHER
Offset:
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
0x1024
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
W
Reserved, must be cleared.
When this bit is set, FEC is enabled, and reception and transmission are possible. When this bit is cleared,
reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted
frame. The buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. When
ETHER_EN is cleared, the DMA, buffer descriptor, and FIFO control logic are reset, including the buffer descriptor
and FIFO pointers. Hardware alters the ETHER_EN bit under the following conditions:
When this bit is set, the equivalent of a hardware reset is performed but it is local to the FEC. ECR[ETHER_EN]
is cleared and all other FEC registers take their reset values. Also, any transmission/reception currently in progress
is abruptly aborted. This bit is automatically cleared by hardware during the reset sequence. The reset sequence
takes approximately eight internal bus clock cycles after this bit is set.
R
MII Management Frame Register (MMFR)
• ECR[RESET] is set by software, in which case ETHER_EN is cleared
• An error condition causes the EIR[EBERR] bit to set, in which case ETHER_EN is cleared
0x1040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ST
OP
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 17-7. MII Management Frame Register (MMFR)
PA
Figure 17-6. Ethernet Control Register (ECR)
Table 17-9. ECR Field Descriptions
RA
Description
TA
8
7
DATA
8
6
7
Access: User read/write
5
Fast Ethernet Controller (FEC)
6
4
Access: User read/write
5
3
4
2
3
_EN
2
0
1
1
RESET
0
17-13
0
0
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