MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 389
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MCF5281CVM66J
Manufacturer Part Number
MCF5281CVM66J
Description
IC MPU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5281CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5281CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1
2
3
4
5
6
20.7
Reset initializes the GPT registers to a known startup state as described in
and
20.8
Table 20-24
20.8.1
A channel flag is set when an input capture or output compare event occurs. Clear a channel flag by writing
a 1 to it.
Freescale Semiconductor
When DDR set the pin as input (0), reading the data register will return the state of the pin. When DDR set the pin as output (1),
reading the data register will return the content of the data latch. Pin conditions such as rising or falling edges can trigger an input
capture on a pin configured as an input.
OMn/OLn bit pairs select the output action to be taken as a result of a successful output compare. When either OMn or OLn is
set and the IOSn bit is set, the pin is an output regardless of the state of the corresponding DDR bit.
Setting an OC3M bit configures the corresponding PORTTn pin to be output. OC3Mn makes the PORTTn pin an output regardless
of the data direction bit when the pin is configured for output compare (IOSn = 1). The OC3Mn bits do not change the state of the
PORTTnDDR bits.
X = Don’t care
An output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction
bit. Enabling output compare disables data register drive of the pin.
A successful output compare on channel 3 causes an output value determined by OC3Dn value to temporarily override the output
compare pin state of any other output compare channel.The next OC action for the specific channel will still be output to the pin.
A channel 3 output compare can cause bits in the output compare 3 data register to transfer to the GPT port data register,
depending on the output compare 3 mask register.
1
1
Registers.”
0
1
Reset
Interrupts
GPT Channel Interrupts (CnF)
lists the interrupt requests generated by the timer.
1
1
Channel 3 IC/OC
Channel 2 IC/OC
Channel 1 IC/OC
Channel 0 IC/OC
PA overflow
PA input
Timer overflow
X
X
Table 20-23. GPT Settings and Pin Functions (continued)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Interrupt Request
X
X
Table 20-24. GPT Interrupt Requests
1
1
Out
Out
PAOVF
Flag
PAIF
C3F
C2F
C1F
C0F
TOF
OC3Dn
OC3Dn
action/
action/
OC
OC
Output compare
compare/
OC3Dn
General Purpose Timer Modules (GPTA and GPTB)
Output
(ch 3)
(ch 3)
Enable Bit
PAOVI
TOI
C3I
C2I
C1I
C0I
PAI
Pin readable only if DDR = 0
Pin driven by channel OC action and
OC3Dn via channel 3 OC
Section 20.5, “Memory Map
(6)
6
20-21
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