MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 597
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MCF5281CVM66J
Manufacturer Part Number
MCF5281CVM66J
Description
IC MPU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5281CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5281CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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A time separator is provided between the triggers and the end of conversion (EOC). The relationship to
QCLK displayed is not guaranteed.
CWPQ1 and CWPQ2 typically lag CWP and only match CWP when the associated queue is inactive.
Another way to view CWPQ1 and CWPQ2 is that these registers update when EOC triggers the write to
the result register.
For the CCW with the pause bit set (CCW0), CWP does not increment until triggered. For the CCW with
the pause bit clear (CCW1), the CWP increments with the EOC.
The conversion results Q1 RESx show the result associated with CCWx, such that R0 represents the result
associated with CCW0.
Figure 28-47
example 1 except:
When the gate closes and opens again, the conversions start with the first CCW in Q1.
When the gate closes, the active conversion completes before the queue goes idle.
When Q1 completes, both the CF1 bit sets and the SSE bit clears.
In this mode, the PF1 bit sets to reflect that a gate closing occurred before the queue completed.
Figure 28-48
assumptions as in
Freescale Semiconductor
•
•
•
CWPQ1
Q1 RES
CONVERSION TIME
TRIG1
QCLK
No pause bits set in any CCW
Externally gated single scan mode for Q1
Single scan enable bit (SSE1) is set.
CWP
EOC
QS
= 14 QCLKS
shows the timing for conversions in externally gated single-scan with same assumptions in
shows the timing for conversions in externally gated continuous scan mode with the same
LAST
0
Figure
Figure 28-46. External Positive Edge Trigger Mode Timing with Pause
LAST
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
28-47.
8
TIME BETWEEN
TRIGGERS
CCW0
4
CCW0
R0
Queued Analog-to-Digital Converter (QADC)
CCW1
CONVERSION TIME
= 14 QCLKS
8
CCW2
CCW1
R1
28-59
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